{"product_id":"logic-design-and-verification-using-systemverilog-revised","title":"Logic Design And Verification Using Systemverilog (Revised)","description":"SystemVerilog is a Hardware Description Language that enables designers to work at the higher levels of logic design abstractions that match the increased complexity of current day integrated circuit and field-programmable gate array (FPGA) designs. The majority of the book assumes a basic background in logic design and software programming concepts. It is directed at: -students currently in an introductory logic design course that also teaches SystemVerilog, -designers who want to update their skills from Verilog or VHDL, and -students in VLSI design and advanced logic design courses that include verification as well as design topics. The book starts with a tutorial introduction on hardware description languages and simulation. It proceeds to the register-transfer design topics of combinational and finite state machine (FSM) design - these mirror the topics of introductory logic design courses. The book covers the design of FSM-datapath designs and their interfaces, including SystemVerilog interfaces. Then it covers the more advanced topics of writing testbenches including using assertions and functional coverage. A comprehensive index provides easy access to the book's topics.The goal of the book is to introduce the broad spectrum of features in the language in a way that complements introductory and advanced logic design and verification courses, and then provides a basis for further learning.Solutions to problems at the end of chapters, and text copies of the SystemVerilog examples are available from the author as described in the Preface.\u003cbr\u003e\u003cul\u003e\n\u003cbr\u003e\u003cli\u003eLibro de impresión bajo demanda\u003c\/li\u003e\n\u003cbr\u003e\u003cli\u003eTiempo promedio de entrega: 21 días\u003c\/li\u003e\n\u003cbr\u003e\u003cli\u003eNuevo y sellado\u003c\/li\u003e\n\u003cbr\u003e\n\u003c\/ul\u003e","brand":"Createspace Independent Publishing Platform","offers":[{"title":"Default Title","offer_id":41121301594155,"sku":"9781523364022","price":4073.0,"currency_code":"MXN","in_stock":true}],"thumbnail_url":"\/\/cdn.shopify.com\/s\/files\/1\/2321\/9467\/files\/0f0f6927-7cba-456a-828c-2fc49140ae92.jpg?v=1774036743","url":"https:\/\/cadabrabooks.com\/es-us\/products\/logic-design-and-verification-using-systemverilog-revised","provider":"Cadabra \u0026 Books","version":"1.0","type":"link"}